By Woogeun Rhee (auth.), Arthur van Roermund, Michiel Steyaert, Johan H. Huijsing (eds.)
This ebook comprises the contribution of 18 tutorials of the twelfth Workshop on Advances in Analog Circuit layout. it truly is quantity 12 within the profitable sequence of Analog Circuit layout, offering worthwhile details and ideal overviews of analog circuit layout, CAD, and RF structures. The sequence should be obvious as a connection with these excited about analog and mixed-signal layout.
Each e-book discusses 3 particular issues on new and priceless layout rules within the zone of analog circuit layout. every one subject is mentioned by means of six specialists within the box and cutting-edge info is shared and overviewed. during this twelfth version the subjects are Fractional-N Synthesizers, layout for Robustness, and Line and Bus Drivers.
Analog Circuit Design is a necessary reference resource for analog layout engineers and researchers that desire to preserve abreast with the most recent advancements within the box. the educational assurance additionally makes it appropriate to be used in a complicated layout path.
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Additional info for Analog Circuit Design: Fractional-N Synthesizers, Design for Robustness, Line and Bus Drivers
Song, “Integrated RF receiver front ends and frequency synthesizers for wireless,” Emerging Technologies: Designing Low Power Digital Systems, International Symp. on Circuits and Systems, May 1996. V. Reinhardt, “Spur reduction techniques in direct digital synthesizers,” in Proceedings of 47th Frequency Control Symposium, Oct. 1993, pp. 230241. W. Rhee and A. Ali, “An on-chip phase-compensation technique in fractional-N frequency synthesis,” in IEEE Proceedings of ISCAS, vol. 3, May 1999, pp. 363-366.
7). Mismatch in the up and down current sources, resulting in gain mismatch for positive and negative phase errors is modeled by The occurrence of a dead zone is modeled by DZ[k]. The current noise spectrum is modeled as a phase noise source which is subjected to its corresponding closed loop transfer function. The non-linear conversion from voltage to frequency/phase in the VCO is modeled by the variation of the VCO gain, when changing the operating point of the PLL. The total analysis time is approximately 15 seconds on a Pentium4.
2. Figure 15 displays the resulting closed loop step response and pole/zero locations due to the above open loop parameter variations. The step response plots allow us to quickly assess that the system has no stability issues over the range of parameter variations entered. The pole/zero locations also confirm that the system remains stable as evidenced by the fact that the poles remain in the left half of the S-plane. Note that the user can effectively do root locus plots as a function of open loop gain or other open loop parameters with this feature.